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1 8 mbit / 16 mbit (x16) multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ? 2000 silicon storage technology, inc.the sst logo and superflash are registered trademarks of silicon storage technology, inc . mpf is a trademark of silicon storage technology, inc. 399-02 2/00 these specifications are subject to change without notice. features: ? organized as 512k x16 / 1m x16 ? single voltage read and write operations - 3.0-3.6v for sst39lf800/160 - 2.7-3.6v for sst39vf800/160 ? superior reliability - endurance: 100,000 cycles (typical) - greater than 100 years data retention ? low power consumption: - active current: 15 ma (typical) - standby current: 4 a (typical) - auto low power mode: 4 a (typical) ? sector-erase capability - uniform 2 kword sectors ? block-erase capability - uniform 32 kword blocks ? fast read access time: - 55 ns for sst39lf800/160 - 70 and 90 ns for sst39vf800/160 ? latched address and data ? fast erase and word-program: - sector-erase time: 18 ms (typical) - block-erase time: 18 ms (typical) - chip-erase time: 70 ms (typical) - word-program time: 14 s (typical) - chip rewrite time: 8 seconds (typical) for sst39lf/vf800 15 seconds (typical) for sst39lf/vf160 ? automatic write timing - internal v pp generation ? end-of-write detection - toggle bit - data# polling ? cmos i/o compatibility ? jedec standard - flash eeprom pinouts and command sets ? packages available - 44-pin soic (500mil) - 48-pin tsop (12mm x 20mm) - 48-ball tfbga (8mm x 10mm) product description the sst39lf800/160 and sst39vf800/160 devices are 512k x16 / 1m x16 cmos multi-purpose flash (mpf) manufactured with ssts proprietary, high perfor- mance cmos superflash technology. the split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst39lf800/160 write (program or erase) with a 3.0-3.6v power supply. the sst39vf800/ 160 write (program or erase) with a 2.7-3.6v power supply. these devices conform to jedec standard pinouts for x16 memories. featuring high performance word-program, the sst39lf800/160 and sst39vf800/160 devices pro- vide a typical word-program time of 14 sec.these devices use toggle bit or data# polling to indicate the completion of program operation. to protect against inadvertent write, they have on-chip hardware and soft- ware data protection schemes. designed, manufac- tured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. the sst39lf800/160 and sst39vf800/160 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. for all system applications, they significantly improve performance and reliability, while lowering power consumption. they inherently use less energy during erase and program than alternative flash tech- nologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash tech- nologies. these devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and program times, independent of the number of erase/ program cycles that have occurred. therefore the sys- tem software or hardware does not have to be modified or de-rated as is necessary with alternative flash tech- nologies, whose erase and program times increase with accumulated erase/program cycles. to meet high density, surface mount requirements, the sst39lf800/160 and sst39vf800/160 are offered in 44-pin soic, 48-pin tsop and 48-pin tfbga pack- ages. see figures 1, 2 and 3 for pinouts. device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write sequences. a command is written by asserting we# low while
2 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. the sst39lf800/160 and sst39vf800/160 also have the auto low power mode which puts the device in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 15 ma to typically 4 a. the auto low power mode reduces the typical i dd active read current to the range of 1 ma/mhz of read cycle time. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. read the read operation of the sst39lf800/160 and sst39vf800/160 is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high imped- ance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 4). word-program operation the sst39lf800/160 and sst39vf800/160 are pro- grammed on a word-by-word basis. the program opera- tion consists of three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the pro- gram operation, once initiated, will be completed within 20 s. see figures 5 and 6 for we# and ce# controlled program operation timing diagrams and figure 17 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. sector/block-erase operation the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. the sst39lf800/160 and sst39vf800/ 160 offer both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uniform block size of 32 kword. the sector-erase operation is initiated by executing a six-byte command sequence with sector- erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by ex- ecuting a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. see figures 10 and 11 for timing waveforms. any commands issued during the sector- or block-erase operation are ignored. chip-erase operation the sst39lf800/160 and sst39vf800/160 provide a chip-erase operation, which allows the user to erase the entire memory array to the 1 state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 9 for timing diagram, and figure 20 for the flowchart. any commands issued during the chip-erase operation are ignored. write operation status detection the sst39lf800/160 and sst39vf800/160 provide two software means to detect the completion of a write (pro- gram or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of- write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase opera- tion. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software rou- tine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
3 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data# polling (dq 7 ) when the sst39lf800/160 and sst39vf800/160 are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. the device is then ready for the next operation. during internal erase operation, any attempt to read dq7 will produce a 0. once the internal erase operation is completed, dq7 will produce a 1. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for data# polling timing diagram and figure 18 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 for toggle bit timing diagram and figure 18 for a flowchart. data protection the sst39lf800/160 and sst39vf800/160 provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst39lf800/160 and sst39vf800/160 provide the jedec approved software data protection scheme for all data alteration operations, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. these devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid com- mands will abort the device to read mode within t rc . the contents of dq 15 -dq 8 are dont care during any sdp command sequence. common flash memory interface (cfi) the sst39lf800/160 and sst39vf800/160 also contain the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must write three-byte sequence, same as product id entry command with 98h (cfi query command) to address 5555h in the last byte sequence. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 5 through 7. the system must write the cfi exit command to return to read mode from the cfi query mode. product identification the product identification mode identifies the devices as the sst39lf/vf800, sst39lf/vf160 and manufacturer as sst. this mode may be accessed by hardware or software operations. the hardware operation is typically used by a programmer to identify the correct algorithm for the sst39lf800/160 and sst39vf800/160. users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. for details, see table 3 for hardware operation or table 4 for software operation, figure 12 for the software id entry and read timing diagram and figure 19 for the software id entry command sequence flowchart. product identification mode exit/cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command se- quence, which returns the device to the read operation. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/cfi exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 14 for timing waveform and figure 19 for a flowchart. t able 1: p roduct i dentification t able address data manufacturers code 0000h 00bfh device code sst39lf/vf800 0001h 2781h device code sst39lf/vf160 0001h 2782h 399 pgm t1.0
4 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet y-decoder i/o buffers and data latches 399 ill b1.0 address buffer & latches x-decoder dq 15 - dq 0 memory address oe# ce# we# eeprom cell array control logic f igure 1: p in a ssignments for 48- pin tsop f unctional b lock d iagram f igure 2: p in a ssignments for 48- ball tfbga a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# nc nc nc nc a18 a17 a7 a6 a5 a4 a3 a2 a1 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we# nc nc nc nc a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 399 ill f01.0 standard pinout top view die up sst39lf/vf800 sst39lf/vf160 sst39lf/vf800 sst39lf/vf160 399 ill f02.0 a13 a9 we# nc a7 a3 a12 a8 nc nc a17 a4 a14 a10 nc a18 a6 a2 a15 a11 a19 nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss a b c d e f g h sst39lf/vf160 6 5 4 3 2 1 top view (balls facing down) 399 ill f02b.0 a13 a9 we# nc a7 a3 a12 a8 nc nc a17 a4 a14 a10 nc a18 a6 a2 a15 a11 nc nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss a b c d e f g h sst39lf/vf800 6 5 4 3 2 1 top view (balls facing down)
5 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 3: p in a ssignments for 44- pin soic nc a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# v ss oe# dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc we# a8 a9 a10 a11 a12 a13 a14 a15 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd sst39lf/vf800 399 ill f01a.1 top view die up nc a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# v ss oe# dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 we# a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd sst39lf/vf160 399 ill f01b.1 top view die up t able 3: o peration m odes s election mode ce# oe# we# a9 dq address read v il v il v ih a in d out a in program v il v ih v il a in d in a in erase v il v ih v il x x sector or block address, xxh for chip-erase standby v ih x x x high z x write inhibit x v il x x high z/ d out x xxv ih x high z/ d out x product identification hardware mode v il v il v ih v h manufacturer code (00bf) a ms (2) - a 1 = v il , a 0 = v il device code (1) a ms (2) - a 1 = v il , a 0 = v ih software mode v il v il v ih a in see table 4 note: (1) device code 2781 for sst39lf/vf800 and 2782 for sst39lf/vf160 (2) a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160 399 pgm t3.0 t able 2: p in d escription symbol pin name functions a ms -a 0 address inputs to provide memory addresses. during sector-erase a ms -a 11 address lines will select the sector. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 3.0-3.6v for sst39lf800/160 2.7-3.6v for sst39vf800/160 vss ground nc no connection unconnected pins. note: a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160 399 pgm t2.1
6 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet t able 5: cfi q uery i dentification s tring 1 for sst39lf/vf800 and sst39lf/vf160 address data data 10h 0051h 11h 0052h query unique ascii string qry 12h 0059h 13h 0001h primary oem command set 14h 0007h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h note 1: refer to cfi publication 100 for more details. 399 pgm t5.0 t able 4: s oftware c ommand s equence command 1st bus 2nd bus 3rd bus 4th bus 5th bus 6th bus sequence write cycle write cycle write cycle write cycle write cycle write cycle addr (1) data addr (1) data addr (1) data addr (1) data addr (1) data addr (1) data word-program 5555h aah 2aaah 55h 5555h a0h wa (3) data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x (2) 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x (2) 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5555h aah 2aaah 55h 5555h 90h cfi query entry 5555h aah 2aaah 55h 5555h 98h software id exit/ xxh f0h cfi exit software id exit/ 5555h aah 2aaah 55h 5555h f0h cfi exit notes: (1) address format a 14 -a 0 (hex). addresses a 15, a 16, a 17, and a 18 are dont care for command sequence for sst39lf/vf800. addresses a 15, a 16, a 17, a 18 and a 19 are "don't care" for command sequence for sst39lf/vf160. (2) sa x for sector-erase; uses a ms -a 11 address lines ba x , for block-erase; uses a ms -a 15 address lines a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160 (3) wa = program word address (4) both software id exit operations are equivalent (5) dq 15 - dq 8 are dont care for command sequence (6) with a ms -a 1 =0; sst manufacturer code = 00bfh, is read with a 0 = 0, sst39lf/vf800 device code = 2781h, is read with a 0 = 1. sst39lf/vf160 device code = 2782h, is read with a 0 = 1. a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160 (7) the device does not remain in software product id mode if powered down. 399 pgm t4.0
7 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t able 6: s ystem i nterface i nformation for sst39lf/vf800 and sst39lf/vf160 address data data 1bh 0027h (1) v dd min. (program/erase) 0030h (1) dq7-dq4: volts, dq3-dq0: 100 millivolts 1ch 0036h v dd max. (program/erase) dq7-dq4: volts, dq3-dq0: 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0004h typical time out for word-program 2 n s (2 4 = 16 s) 20h 0000h typical time out for min. size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 0006h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 4 = 32 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 6 = 128 ms) note: (1) 0030h for sst39lf800/160 and 0027h for sst39vf800/160 399 pgm t6.1 t able 7 a : d evice g eometry i nformation for sst39lf/vf800 address data data 27h 0014h device size = 2 n bytes (14h = 20; 2 20 = 1m bytes) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of byte in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = number of sectors; z x 256b = sector size) 2eh 0000h y = 255 + 1 = 256 sectors (00ffh = 255) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbytes/sector (0010h = 16) 31h 000fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 15 + 1 = 16 blocks (000fh = 15) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbytes/block (0100h = 256) 399 pgm t7a.0 t able 7 b : d evice g eometry i nformation for sst39lf/vf160 address data data 27h 0015h device size = 2 n byte (15h = 21; 2 21 = 2m bytes) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of byte in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = number of sectors; z x 256b = sector size) 2eh 0001h y = 511 + 1 = 512 sectors (01ff = 511) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbytes/sector (0010h = 16) 31h 001fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 31 + 1 = 32 blocks (001f = 31) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbytes/block (0100h = 256) 399 pgm t7.0
8 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet absolute maximum stress ratings (applied conditions greater than those listed under absolute maximum stress ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias ......................................................................................................... ........ -55c to +125c storage temperature ............................................................................................................ .......... -65c to +150c d. c. voltage on any pin to ground potential ............................................................................ -0.5v t o v dd + 0.5v transient voltage (<20 ns) on any pin to ground potential ........................................................ -1.0v to v dd + 1.0v voltage on a 9 pin to ground potential ................................................................................................ -0.5v to 13.2v package power dissipation capability (ta = 25c) ............................................................................... ............ 1.0w surface mount lead soldering temperature (3 seconds) ........................................................................... .... 240c output short circuit current (1) ............................................................................................................................... .................................. 50 ma note: (1) outputs shorted for no more than one second. no more than one output shorted at a time. ac c onditions of t est input rise/fall time ......... 5 ns output load ..................... c l = 30 pf for sst39lf800/160 c l = 100 pf for sst39vf800/160 see figures 15 and 16 o perating r ange for sst39lf800/160 range ambient temp v dd commercial 0 c to +70 c 3.0 - 3.6v o perating r ange for sst39vf800/160 range ambient temp v dd commercial 0 c to +70 c 2.7 - 3.6v industrial -40 c to +85 c 2.7 - 3.6v
9 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t able 11: r eliability c haracteristics symbol parameter minimum specification units test method n end (1) endurance 10,000 cycles jedec standard a117 t dr (1) data retention 100 years jedec standard a103 v zap_hbm (1) esd susceptibility 2000 volts jedec standard a114 human body model v zap_mm (1) esd susceptibility 200 volts jedec standard a115 machine model i lth (1) latch up 100 + i dd ma jedec standard 78 note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this par ameter. 399 pgm t12.0 399 pgm t10.0 t able 9: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read (1) power-up to read operation 100 s t pu-write (1) power-up to program/erase 100 s operation note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this parameter . t able 8: dc o perating c haracteristics v dd = 3.0-3.6v for sst39lf800/160 and 2.7-3.6v for sst39vf800/160 limits symbol parameter min max units test conditions i dd power supply current ce#=oe#=v il, we#=v ih , all i/os open, read 20 ma address input = v il /v ih , at f=1/t rc min. program and erase 25 ma ce#=we#=v il, oe#=v ih, v dd =v dd max. i sb standby v dd current 20 a ce#=v ihc , v dd = v dd max. i alp auto low power current 20 a ce#=v ilc , v dd = v dd max., all inputs = v ihc or v ilc , we# = v ihc i li input leakage current 1 a v in =gnd to v dd , v dd = v dd max. i lo output leakage current 1 a v out =gnd to v dd , v dd = v dd max. v il input low voltage 0.8 v v dd = v dd min. v ilc input low voltage (cmos) 0.3 v v dd = v dd max. v ih input high voltage 0.7 v dd vv dd = v dd max. v ihc input high voltage (cmos) v dd -0.3 v v dd = v dd max. v ol output low voltage 0.2 v i ol = 100 a, v dd = v dd min. v oh output high voltage v dd -0.2 v i oh = -100 a, v dd = v dd min. v h supervoltage for a 9 pin 11.4 12.6 v ce# = oe# =v il , we# = v ih i h supervoltage current 200 a ce# = oe# = v il , we# = v ih , a 9 = v h max. for a 9 pin 399 pgm t9.0 t able 10: c apacitance (ta = 25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o (1) i/o pin capacitance v i/o = 0v 12 pf c in (1) input capacitance v in = 0v 6 pf note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this parameter . 399 pgm t11.0
10 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet t able 13: p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph (1) we# pulse width high 30 ns t cph (1) ce# pulse width high 30 ns t ds data setup time 30 ns t dh (1) data hold time 0 ns t ida (1) software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 100 ms note: (1) this parameter is measured only for initial qualification and after the design or process change that could affect this pa rameter. 399 pgm t14.0 ac characteristics t able 12: r ead c ycle t iming p arameters v dd = 3.0-3.6v for sst39lf800/160 and v dd = 2.7-3.6v for sst39vf800/160 sst39lf800/160-55 sst39vf800/160-70 sst39vf800/160-90 symbol parameter min max min max min max units t rc read cycle time 55 70 90 ns t ce chip enable access time 55 70 90 ns t aa address access time 55 70 90 ns t oe output enable access time 30 35 45 ns t clz (1) ce# low to active output 0 0 0 ns t olz (1) oe# low to active output 0 0 0 ns t chz (1) ce# high to high-z output 15 20 30 ns t ohz (1) oe# high to high-z output 15 20 30 ns t oh (1) output hold from address 0 0 0 ns change note: (1) this parameter is measured only for initial qualification and after the design or process change that could affect this pa rameter. 399 pgm t13.1
11 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 4: r ead c ycle t iming d iagram f igure 5: we# c ontrolled p rogram c ycle t iming d iagram 399 ill f03.0 address a ms-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160 399 ill f04.0 address a ms-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160
12 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet f igure 6: ce# c ontrolled p rogram c ycle t iming d iagram f igure 7: d ata # p olling t iming d iagram 399 ill f05.0 address a ms-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160 399 ill f06.0 address a ms-0 dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160
13 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 8: t oggle b it t iming d iagram f igure 9: we# c ontrolled c hip -e rase t iming d iagram 399 ill f07.0 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160 399 ill f08.0 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 13) a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160
14 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet f igure 11: we# c ontrolled s ector -e rase t iming d iagram f igure 10: we# c ontrolled b lock -e rase t iming d iagram 399 ill f17.0 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 50 55 aa 80 aa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# controlled block-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 13) ba x = block address a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160 399 ill f18.0 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 13) sa x = sector address a ms = most significant address a ms = a 18 for sst39lf/vf800 and a 19 for sst39lf/vf160
15 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 12: s oftware id e ntry and r ead f igure 13: cfi q uery e ntry and r ead 399 ill f20.0 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 399 ill f09.1 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 device id = 2781 for sst39lf/vf800 and 2782 for sst39lf/vf160
16 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet f igure 14: s oftware id e xit /cfi e xit 399 ill f10.0 address a 14-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# aa 55 f0
17 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 15: ac i nput /o utput r eference w aveforms f igure 16: a t est l oad e xample ac test inputs are driven at v iht (0.9 v dd ) for a logic 1 and v ilt (0.1 v dd ) for a logic 0. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). inputs rise and fall times (10% ? 90%) are <5 ns. note: v it Cv input test v ot Cv output test v iht Cv input high test v ilt Cv input low test 399 ill f11.1 reference points output input v it v iht v ilt v ot 399 ill f12.1 to tester to dut c l
18 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet f igure 17: w ord -p rogram a lgorithm 399 ill f13.0 start load data: aa address: 5555 load data: 55 address: 2aaa load data: a0 address: 5555 load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
19 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 18: w ait o ptions 399 ill f14.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
20 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet f igure 19: s oftware p roduct id/cfi c ommand f lowcharts 399 ill f15.0 load data: xxaa address: 5555 software product id entry command sequence load data: xx55 address: 2aaa load data: xx90 address: 5555 wait t ida read software id load data: xxaa address: 5555 cfi query entry command sequence load data: xx55 address: 2aaa load data: xx98 address: 5555 wait t ida read cfi data load data: xxaa address: 5555 software id exit/cfi exit command sequence load data: xx55 address: 2aaa load data: xxf0 address: 5555 load data: xxf0 address: xx return to normal operation wait t ida wait t ida return to normal operation
21 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 20: e rase c ommand s equence 399 ill f16.0 load data: xxaa address: 5555 chip-erase command sequence load data: xx55 address: 2aaa load data: xx80 address: 5555 load data: xx55 address: 2aaa load data: xx10 address: 5555 load data: xxaa address: 5555 wait t sce chip erased to ffffh load data: xxaa address: 5555 sector-erase command sequence load data: xx55 address: 2aaa load data: xx80 address: 5555 load data: xx55 address: 2aaa load data: xx30 address: sa x load data: xxaa address: 5555 wait t se sector erased to ffffh load data: xxaa address: 5555 block-erase command sequence load data: xx55 address: 2aaa load data: xx80 address: 5555 load data: xx55 address: 2aaa load data: xx50 address: ba x load data: xxaa address: 5555 wait t be block erased to ffffh
22 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet device speed suffix1 suffix2 sst39xfxxx - xxx - xx - xx package modifier j = 44 pins k = 48 pins numeric = die modifier package type e = tsop (12mm x 20mm) b = tfbga (0.8 mm pitch; 8mm x 10mm) s = soic (500 mil) temperature range c = commercial = 0 to 70c i = industrial = -40 to 85c minimum endurance 4 = 10,000 cycles read access speed 55 = 55 ns, 70 = 70 ns, 90 = 90 ns device density 800 = 8 megabit 160 = 16 megabit voltage l = 3.0-3.6v v = 2.7-3.6v sst39lf800 valid combinations sst39lf800-55-4c-ek sst39lf800-55-4c-bk sst39lf800-55-4c-sj sst39vf800 valid combinations sst39vf800-70-4c-ek sst39vf800-70-4c-bk sst39vf800-70-4c-sj sst39vf800-90-4c-ek sst39vf800-90-4c-bk sst39vf800-90-4c-sj sst39vf800-70-4i-ek sst39vf800-70-4i-bk sst39vf800-70-4i-sj sst39vf800-90-4i-ek sst39vf800-90-4i-bk sst39vf800-90-4i-sj sst39lf160 valid combinations sst39lf160-55-4c-ek sst39lf160-55-4c-bk sst39lf160-55-4c-sj sst39vf160 valid combinations sst39vf160-70-4c-ek sst39vf160-70-4c-bk sst39vf160-70-4c-sj sst39vf160-90-4c-ek sst39vf160-90-4c-bk SST39VF160-90-4C-SJ sst39vf160-70-4i-ek sst39vf160-70-4i-bk sst39vf160-70-4i-sj sst39vf160-90-4i-ek sst39vf160-90-4i-bk sst39vf160-90-4i-sj example: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations.
23 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 packaging diagrams 48-p in t hin s mall o utline p ackage (tsop) 12 mm x 20 mm sst p ackage c ode : ek 48-b all t hin p rofile f ine - pitch b all g rid a rray (tfbga) 8 mm x 10 mm sst p ackage c ode : bk 48.tsop-ek-ill.4 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 12.20 11.80 .270 .170 1.05 0.95 . 50 bsc 0.15 0.05 18.50 18.30 20.20 19.80 0.70 0.50 pin # 1 identifier a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.21 0.05 1.10 0.10 0.15 8.00 0.20 0.30 0.05 (48x) a1 corner 10.00 0.20 0.80 4.00 0.80 5.60 48ba tfbga.bk8x10-ill.7 note: 1. complies with the general requirements of jedec publication 95 mo-210, although some dimensions may be more stringent. (this specific outline variant has not yet been registered) 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm.
24 ? 2000 silicon storage technology, inc. 399-02 2/00 8 mbit / 16 mbit multi-purpose flash sst39lf800 / sst39lf160 / sst39vf800 / sst39vf160 data sheet silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.ssti.com ? literature faxback 888-221-1178, international 732-544-2873 44-p in s mall o utline ic (soic/500 mil ) sst p ackage c ode : sj 44.soic500mil-sj-ill.2 .33 .51 1.27 .10 .30 2.72 3.00 .19 .25 45? 0.47 1.15 0? 8? 28.30 28.70 15.74 16.34 12.45 12.70 pin #1 identifier note: 1. all linear dimensions are in millimeters (min/max). 2. coplanarity: 0.1 (.05) mm.

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